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Preliminary
PLL502-12
96MHz - 200MHz Low Phase Noise LVDS VCXO (12 - 25MHz Crystals)
FEATURES
* * * * * * * * Low phase noise output for the 96MHz to 200MHz range (-125 dBc at 10kHz offset). LVDS output. 12 to 25MHz crystal input. Integrated crystal load capacitor: no external load capacitor required. Output Enable selector. Wide pull range (min. +/-190 ppm) 3.3V operation. Available in 16 Pin TSSOP or SOIC.
PIN CONFIGURATION
VDD VDD XIN XOUT OE VIN GND
1 2
16 15
VDD GND_BUF CLKBAR VDD_BUF CLK GND_BUF GND GND
PLL 502-12
3 4 5 6 7 8
14 13 12 11 10 9
DESCRIPTION
The PLL502-12 is a monolithic low jitter and low phase noise (-125dBc/Hz @ 10kHz offset) VCXO IC with LVDS output, for 96MHz to 200MHz output range. It allows the control of the output frequency with an input voltage (VIN), using a low cost crystal. The chip provides a pullable output at a frequency of F XIN x 8. This makes the PLL502-12 ideal for a wide range of applications, including 155.52MHz for SONET.
GND
F OUT = F XIN x 8
OE (Pin 5) 0 1 (Default)
Output State Tri-state Output enabled
BLOCK DIAGRAM
VCO Divider
Reference Divider
Phase Comparator
Charge Pump
Loop Filter
VCO
CLKBAR CLK
XIN XOUT
XTAL OSC VARICAP
OE
VIN
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 7/15/02 Page 1
Preliminary
PLL502-12
96MHz - 200MHz Low Phase Noise LVDS VCXO (12 - 25MHz Crystals)
PIN DESCRIPTIONS
Name VDD XIN XOUT OE VIN GND GND_BUF CLK VDD_BUF CLKB Number 1,2,16 3 4 5 6 7,8,9,10 11,15 12 13 14 Type P I I I I P P O P O Crystal input pin. Crystal output pin. Output enable input pin. Disables (tri-state) output when low. Internal pull-up enables output by default if pin is not connected to low. Frequency control voltage input pin. GND Power connectors. GND connector for output buffers. True clock output pin. +3.3V Power supply connector for output buffers. Complementary clock output pin. Description +3.3V Power supply connectors.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings PARAMETERS Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection SYMBOL V DD VI VO TS TA TJ V SS -0.5 V SS -0.5 -65 -40 MIN. MAX. 7 V DD +0.5 V DD +0.5 150 85 125 260 2 UNITS V V V C C C C kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for INDUSTRIAL grade only.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 7/15/02 Page 2
Preliminary
PLL502-12
96MHz - 200MHz Low Phase Noise LVDS VCXO (12 - 25MHz Crystals)
2. Crystal Specifications PARAMETERS Crystal Resonator Frequency Crystal Loading Rating Crystal Pullability Recommended ESR SYMBOL F XIN C L (xtal) C 0 /C 1 (xtal) RE CONDITIONS Parallel Fundamental Mode At VIN = 1.65V
AT cut
MIN. 12
TYP.
MAX. 25
UNITS MHz pF
9.5 250 30
AT cut
Note: Crystal Loading rating: 9.5pF is the loading the crystal sees from the VCXO chip at VIN = 1.65V. It is assumed that the crystal will be at nominal frequency at this load. If the crystal requires more load to be at nominal frequency, the additional load must be added externally. This however may reduce the pull range.
3. Voltage Control Crystal Oscillator PARAMETERS
VCXO Stabilization Time *
SYMBOL
T VCXOSTB
CONDITIONS
From power valid
MIN.
TYP.
10
MAX.
UNITS
ms
VCXO Tuning Range CLK output pullability Linearity
VCXO Tuning Characteristic VCON pin input impedance VCON modulation BW
F XIN = 12 - 25MHz; XTAL C 0 /C 1 < 250 0V VCON 3.3V
380 190 5
115
ppm ppm 10 %
ppm/V k kHz
2000
0V VCON 3.3V, -3dB
25
Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
4. General Electrical Specifications PARAMETERS Supply Current, Dynamic (with Loaded Outputs) Operating Voltage Output Clock Duty Cycle Short Circuit Current SYMBOL I DD V DD @ 1.25V (LVDS) LVDS 3.13 45 50 50 CONDITIONS MIN. TYP. MAX. 60 3.47 55 UNITS mA V % mA
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 7/15/02 Page 3
Preliminary
PLL502-12
96MHz - 200MHz Low Phase Noise LVDS VCXO (12 - 25MHz Crystals)
5. Jitter and Phase Noise specification PARAMETERS Period jitter RMS at 155MHz Accumulated jitter RMS at 155MHz Integrated jitter RMS at 155MHz Phase Noise relative to carrier Phase Noise relative to carrier Phase Noise relative to carrier Phase Noise relative to carrier Phase Noise relative to carrier
Note: Phase Noise measured at VIN = 0V
CONDITIONS With capacitive decoupling between VDD and GND. With capacitive decoupling between VDD and GND. Over 10,000 cycles. Integrated 12 kHz to 20 MHz 155MHz @10Hz offset 155MHz @100Hz offset 155MHz @1kHz offset 155MHz @10kHz offset 155MHz @100kHz offset
MIN.
TYP. 9 TBM 3 -60 -90 -112 -125 -123
MAX.
UNITS ps ps
4
ps dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
6. LVDS Electrical Characteristics PARAMETERS Output Differential Voltage V DD Magnitude Change Output High Voltage Output Low Voltage Offset Voltage Offset Magnitude Change Power-off Leakage Output Short Circuit Current SYMBOL V OD V OD V OH V OL V OS V OS I OXD I OSD V out = V DD or GND V DD = 0V R L = 100 (see figure) CONDITIONS MIN. 247 -50 1.4 0.9 1.125 0 1.1 1.2 3 1 -5.7 1.375 25 10 -8 TYP. 355 MAX. 454 50 1.6 UNITS mV mV V V V mV uA mA
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 7/15/02 Page 4
Preliminary
PLL502-12
96MHz - 200MHz Low Phase Noise LVDS VCXO (12 - 25MHz Crystals)
7. LVDS Switching Characteristics PARAMETERS Differential Clock Rise Time Differential Clock Fall Time
LVDS Levels Test Circuit
OUT
SYMBOL
tr tf
CONDITIONS R L = 100 C L = 10 pF (see figure)
MIN. 0.2 0.2
TYP. 0.7 0.7
MAX. 1.0 1.0
UNITS ns ns
LVDS Switching Test Circuit
OUT
50
CL = 10pF
VOD
VOS
VDIFF
RL = 100
50 CL = 10pF OUT OUT
LVDS Transistion Time Waveform
OUT 0V (Differential) OUT
80% V DIFF 20% 0V
80%
20%
tR
tF
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 7/15/02 Page 5
Preliminary
PLL502-12
96MHz - 200MHz Low Phase Noise LVDS VCXO (12 - 25MHz Crystals)
PACKAGE INFORMATION
16 PIN Narrow SOIC, TSSOP ( mm )
SOIC Symbol A A1 B C D E H L e Min. 1.35 0.10 0.33 0.19 9.80 3.80 5.80 0.40 1.27 BSC Max. 1.75 0.25 0.51 0.25 10.00 4.00 6.20 1.27 0.45 Min. 0.05 0.19 0.09 4.90 4.30 TSSOP Max. 1.20 0.15 0.30 0.20 5.10 4.50 6.40 BSC 0.75 0.65 BSC B e A1 C L A D E H
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991
The order number for this device is a combination of the following: Device number, Package type and Operating temperature range
PART NUMBER
PLL502-12 S C XX
PART NUMBER
REVISION CODE (when applicable) C=COMMERCIAL M=MILITARY
TEMPERATURATURE
I=INDUSTRAL
PACKAGE TYPE
S=SOIC, O=TSSOP
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 7/15/02 Page 6

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